
/* Master Clock = 88 MHz */
#define M_CLK (88000000UL) 


/* ST0299 Registers addresses definition */
#define  REG_ID             0x00    /* Identification Register R */
#define  REG_RCR            0x01    /* Reference Clock Register */
#define  REG_MCR            0x02    /* Master Clock Register */
#define  REG_ACR            0x03    /* Auxiliary Clock Register */
#define  REG_F22FR          0x04    /* F22 Frequency Register */
#define  REG_I2CRPT         0x05    /* I2CRPT Register */
#define  REG_DACR1          0x06    /* DAC Register MSB */
#define  REG_DACR2          0x07    /* DAC Register LSB */
#define  REG_DISEQC         0x08    /* DISEQC and Lock Control Register */
#define  REG_DISEQC_FIFO    0x09    /* DISEQC FIFO */
#define  REG_DISEQC_STATUS  0x0A    /* DISEQC STATUS */
#define  REG_IOCFG          0x0C    /* Input/Output Configuration Register */
#define  REG_AGC1C          0x0D    /* AGC Control Register */
#define  REG_RTC            0x0E    /* Timing Loop Register */
#define  REG_AGC1R          0x0F    /* AGC1 Reference Register */
#define  REG_AGC2O          0x10    /* AGC2 and Offset Control Register */
#define  REG_TLSR           0x11    /* Timing Lock Setting Register */
#define  REG_CFD            0x12    /* Carrier Frequency Detector Register */
#define  REG_ACLC           0x13    /* Alpha Carrier and Noise Estimator Register */
#define  REG_BCLC           0x14    /* Betaa Carrier Register */
#define  REG_CLDT           0x15    /* Carrier Lock Detector Threshold Register */
#define  REG_AGC1I          0x16    /* AGC1 Integrator Register */
#define  REG_TLIR           0x17    /* Timing Lock Indicatir Register */
#define  REG_AGC2I1         0x18    /* AGC2 Integrator Register (MSB) */
#define  REG_AGC2I2         0x19    /* AGC2 Integrator Register (LSB) */
#define  REG_RTF            0x1A    /* Timing Frequency Register */
#define  REG_VSTATUS        0x1B    /* VStatus Register */
#define  REG_CLDI           0x1C    /* Carrier Lock Detector Value Register */
#define  REG_ERRCNT_HIGH    0x1D    /* Error Count Register MSB */
#define  REG_ERRCNT_LOW     0x1E    /* Error Count Register LSB */
#define  REG_SFRH           0x1F    /* Symbol Frequency Register */
#define  REG_SFRM           0x20    /* Symbol Frequency Register */
#define  REG_SFRL           0x21    /* Symbol Frequency Register */
#define  REG_CFRM           0x22    /* Carrier Frequency Register */
#define  REG_CFRL           0x23    /* Carrier Frequency Register */
#define  REG_NIRH           0x24    /* Noise Indicator Register */
#define  REG_NIRL           0x25    /* Noise Indicator Register */
#define  REG_VERROR         0x26    /* VError Register */
#define  REG_FECM           0x28    /* FEC Mode Register */
#define  REG_VTH0           0x29    /* Viterbi Threshold Register */
#define  REG_VTH1           0x2A    /* Viterbi Threshold Register */
#define  REG_VTH2           0x2B    /* Viterbi Threshold Register */
#define  REG_VTH3           0x2C    /* Viterbi Threshold Register */
#define  REG_VTH4           0x2D    /* Viterbi Threshold Register */
#define  REG_PR             0x31    /* Puncture Rate and Synchro Register */
#define  REG_VSEARCH        0x32    /* Viterbi and Synchro Search Register */
#define  REG_RS             0x33    /* RS Control Register */
#define  REG_ERRCNT         0x34    /* Error Control Register */

#define INRANGE(X,Y,Z) (((X<=Y) && (Y<=Z))||((Z<=Y) && (Y<=X)) ? 1 : 0)     

/* the lookup table */
typedef struct
{
	int realval;	/*	real value */
	int regval;		/*	register value (C/N estimator value or AGC1 integrator value )	*/
} LOOKPOINT;

